Title: Mitigating the Sim-to-Real Discrepancy in Semiconductor Visual Program Synthesis Through Input Binarization

Abstract:

Accurate parametric control of circuit geometry is critical for semiconductor inspection; however, acquiring adequate real-world training data is prohibitively expensive. While generative approaches like Generative Adversarial Networks (GANs) and diffusion models can expand training datasets, they fail to provide the nanometer-level geometric precision necessary for metrology. To address this, we introduce a visual program synthesis framework where a Vision-Language Model (VLM) transforms inspection images into editable Domain-Specific Language (DSL) code. This code delineates circuit geometries, facilitating the controlled generation of training data through precise parameter adjustment. Since the VLM is trained exclusively on synthetic data rendered via DSL, a domain gap emerges when the model processes actual Scanning Electron Microscope (SEM) images. We close this gap by implementing an input binarization technique that removes SEM-specific textures and noise, allowing the model to concentrate on structural geometry. Testing on the MIIC dataset reveals that binarized inputs raise the mean Dice coefficient from 0.4393 to 0.5256 compared to the raw-input baseline. These results indicate that straightforward texture abstraction effectively reduces the sim-to-real gap.

Source: arXiv Generated at: 2026-06-02 00:00:00 UTC