Title: Enhancing Probabilistic Circuits with Geometry Awareness Through Voronoi Tessellations

Abstract:

While Probabilistic Circuits (PCs) facilitate efficient and exact inference, their reliance on mixture weights that are independent of the data restricts their capacity to model the local geometric properties of the data manifold. To address this limitation, we propose integrating Voronoi tessellations (VT) directly into the sum nodes of a PC, thereby embedding geometric structure naturally. However, the straightforward application of this structure compromises computational tractability. We rigorously define this incompatibility and present two distinct solutions: first, an approximate inference method that ensures strict lower and upper bounds for the inference process; and second, a specific structural condition for VT that restores exact and tractable inference. Additionally, we devise a differentiable relaxation for VT to facilitate gradient-based optimization, demonstrating the effectiveness of our approach through empirical evaluations on conventional density estimation benchmarks.

Source: arXiv Generated at: 2026-06-02 00:00:00 UTC