Title: CRAM-ER: An Error-Resilient Spintronic Computational Random Access Memory Architecture for Scalable In-Memory Processing

Abstract:

While Deep Neural Networks (DNNs) currently deliver state-of-the-art results across a wide array of applications, conventional Von Neumann computing architectures are hindered by significant memory bottlenecks. Although near-memory and compute-in-memory strategies offer solutions to these constraints, they often introduce substantial peripheral overhead. Computational Random Access Memory (CRAM) utilizing MRAM technology provides a distinct advantage by enabling in-situ logic operations without such overhead, thereby delivering a solution that is both energy-efficient and dense. Nevertheless, the probabilistic nature of MRAM switching leads to gate-level errors, which compromises the reliability and scalability of CRAM systems when accelerating DNN workloads. Additionally, the requirement for numerous sequential MRAM write operations severely limits CRAM throughput.

To overcome these limitations, this study introduces CRAM-ER, an error-resilient CRAM architecture designed to facilitate scalable in-memory matrix-vector multiplications (MVMs). Our approach employs a hardware-software co-design framework that is aware of errors, utilizing a hybrid architecture that combines spintronic-CRAM with a CMOS adder-tree. This configuration effectively mitigates device-level errors while demonstrating high efficiency in terms of both energy consumption and area usage. Furthermore, we implement error-aware model fine-tuning alongside fine-grained error correction mechanisms to bolster error resilience. Performance evaluations of this CMOS-spintronic hybrid architecture on DNN benchmarks reveal near-lossless accuracy. Notably, the system reduces CRAM latency by up to two orders of magnitude and surpasses traditional CPU/GPU setups paired with high-bandwidth DRAM in both energy efficiency and energy-delay product metrics.

Source: arXiv Generated at: 2026-06-03 00:00:00 UTC