Title: Mitigating and Understanding the Impact of Short- and Long-Term Transistor Aging in Deep Neural Networks

Abstract:

Deep neural networks (DNNs) are widely deployed in practical applications such as speech recognition and image classification. However, when these networks are implemented on hardware within integrated circuits (ICs), their inference accuracy suffers from degradation caused by transistor aging. This aging process reduces transistor switching speeds, which can lead to system-level timing violations if the clock signals become unsustainable. To ensure reliability throughout the device's projected lifespan, engineers typically incorporate guardbands to avert these timing errors. Nevertheless, employing excessively large guardbands inevitably results in significant performance penalties, such as reduced throughput or speed.

This chapter offers an in-depth analysis of how both short-term and long-term transistor aging affect the inference accuracy of DNNs. To counteract these accuracy losses and maintain performance, we introduce a methodology for aging-aware retraining. This approach generates DNNs that remain resilient even when aggressive, or smaller-than-necessary, guardbands are utilized. Consequently, this strategy enhances the inference accuracy of DNNs despite the presence of aging-induced degradation. The chapter explores these phenomena and their corresponding mitigation strategies, specifically within the context of a hardware implementation of a DNN designed for image classification on a standard dataset. Additionally, the text briefly examines the use of short-term aging as an excitation mechanism for identifying hardware Trojans within integrated circuits.

Source: arXiv Generated at: 2026-06-04 00:00:00 UTC